1. Field of the Invention
The present invention relates to a substrate for a semiconductor integrated circuit such as LSI and a method of manufacturing the same and, more particularly, to element isolation technique for a semiconductor integrated circuit.
2. Description of the Prior Art
To fabricate an LSI, it is necessary to form element isolation regions for electrically isolating one device region from another device region around respective device regions in which active elements such as transistor or passive elements such as resistor, capacitor, etc. are arranged. In the development of MOSLSI technology and bipolar LSI technology, element isolation technique for forming the element isolation region has been always one of important technical themes. Importance of such element isolation technique would be increased more and more in future. One epoch-making development in the history of the element isolation technique was LOCOS (LOCal Oxidation of Silicon) technique capable of partitioning the device region and the element isolation region in a self-aligned manner. In LOCOS technique (LOCOS method), as shown in FIG. 1, selective oxidation is effected using a nitride (Si.sub.3 N.sub.4) film 88 as a mask, and an oxide film (SiO.sub.2 film) 82 formed on a Si surface without Si.sub.3 N.sub.4 film 88 is then used as an insulating layer (such as a field oxide layer) for the element isolation region. It is not too much to say that prosperity of LSI industry of the day is brought out by the LOCOS technique. However, with the drive to manufacture ever more complex and fine pattern in the order of submicron to deep submicron, this LOCOS technology is coming up to the limit. The greatest problems are lateral encroachment of the device region (active region) due to so-called bird's beak and generation of crystal defects due to local stress caused when the field oxide film is formed. Especially the bird's beak serves as an impediment factor in high integration for VLSI or ULSI, a thickness of the oxide film 82 must be thinned to lessen encroachment due to the bird's beak and to accelerate miniaturization. However, if the thickness of the oxide film 82 is made thin, the problem to lower the device breakdown voltage arises. In order to overcome this problem, various improvements of LOCOS method and novel isolation techniques have been proposed. For example, as improved element isolation techniques based on the LOCOS method, improved coplanar method, direct nitride film mask method, SWAMI (Side WAll Masked Isolation), and so on have been known. Further, selective epitaxial method, U-groove method, and the like have been proposed. In addition to these element isolation techniques, an oxide film burying method called BOX (Buried OXide) method and shown in FIG. 2 is given attention as element isolation technique for VLSI, etc. on the order of submicron and deep submicron. In the oxide film burying method, after U-grooves are formed in a silicon substrate 5, insulating material 77 such as SiO.sub.2 is deposited by CVD method, or the like to bury into the U-grooves.
In insulating film deposition technique used in BOX method, various requirements such as uniformity, planarization, step coverage, film quality, low temperature in process, and the like are imposed. In particular, step coverage and low temperature in process are important. In manufacturing the semiconductor device such as giga scale integration circuit (GSI) which requires accelerated high integration more and more, the low temperature insulating film with high quality is required. In response to this requirement, LTO (Low Temperature Oxide) film which is deposited by CVD technique using monosilane (SiH.sub.4), N.sub.2 O, etc. formed at relatively low temperature (300 to 450.degree. C.) has been known in the prior art. In general, but according to conditions, LTO oxide film has poor step coverage and is inferior in film quality. The oxide film formed by atmospheric pressure CVD or low pressure CVD exhibits tensile stress and therefore has small crack immunity.
In view of these requirements, recently CVD technique using organic silicon based material representative of TEOS (tetraethylorthosilicate; Si(OC.sub.2 H.sub.5).sub.4) has been researched positively. This is because, for example, the insulating film can be formed at low temperature of less than 450.degree. C. by virtue of reaction between TEOS and O.sub.3 and step coverage is excellent.
In BOX method shown in FIG. 2, the grooves (trenches) having a relatively shallow depth, called shallow trench isolation (STI) method, is of advantage for miniaturization. Although this STI method is advantageous in a respect of miniaturization compared to the LOCOS method, stress is caused in the semiconductor substrate by annealing in LSI manufacturing step--during or after forming the element isolation region--due to thermal expansion coefficient mismatch between the semiconductor substrate (such as silicon) in which active elements, etc. are formed and the insulating material (e.g., silicon oxide) to be buried in the grooves. The thermal expansion coefficient mismatch generates crystalline defects such as dislocation 12 as shown by thick solid lines in FIG. 2. In particular, in case the silicon oxide is formed by organic silicon source, it is difficult in the existing state to obtain high purity organic silicon source because of limitation in a material refining technique for the organic silicon source. Therefore, impurities (e.g., H.sub.2 O, adulterant organic substance) other than silicon oxide (SiO.sub.2) remain or are absorbed immediately after the silicon oxide is deposited.
For this reason, various problems are caused since these impurities are dissociated by succeeding annealing at 800 to 1000.degree. C. Usually moisture is included at 100 to 20 ppm as an impurity in the organic silicon source material. For this reason, in the silicon device, for example, excessive compressive stress is applied to the silicon substrate due to film shrinkage caused by dissociation of moisture included in the buried oxide film as well as difference of thermal expansion coefficient between the silicon substrate and buried SiO.sub.2 (buried oxide film). Furthermore, in the conventional STI structure shown in FIG. 2, crystal defects are readily introduced into the substrate in thermal process in device manufacturing steps during or after forming the element isolation region. That is, in the conventional element isolation technique based on the STI method using organic silicon source, there are problems of generation, amplification, and propagation of crystalline defects such as dislocation 12. And electric characteristics such as the breakdown voltages, junction leakage currents and carrier lifetime are readily degraded since a lot of crystalline defects are generated in the device region (active layer region), and metal impurities are easily trapped by these crystalline defects. These defects degrade memory retention characteristics.
In particular, in actual LSI manufacturing processes, there are caused stress caused by the element isolation region and another stress caused by damage generated ion implantation and caused by various multilayer films such as metal electrode film, interlayer insulating film, and the like having different purposes, so that crystalline defects easily occur. In addition, a synergistic effect between crystalline defects due to the STI structure and crystalline defects due to other reasons appears, and crystalline defects caused in the substrate easily trap metal impurities. For this reason, in the conventional STI method, owing to presence of crystalline defects in the active layer (device region), junction leakage current is increased and electric failures such as low dielectric breakdown voltage of the gate oxide film are caused. Accordingly, development of element isolation technique not to generate crystalline defects in the device region is an important theme to be solved in future miniaturized LSI manufacturing.
In summary, in the element isolation technique required for miniaturized GSI, ULSI, VLSI, and the like, various requirements such as bird's-beak-free, crystalline-defect-free isolation, surface evenness (planar surface), and so on are needed. In the STI method, there is no trouble concerning bird's beak, but surface evenness and suppression of the crystalline defects still remain as the important subject to be solved.